Miniaturization of electronic components has been an important goal of engineers. Various products ranging from liquid crystal display (LCD) panels to inkjet print heads are evidence of their success. These products provide dazzling results while reducing the overall footprint of the product.
However, miniaturized products are often expensive because they are difficult to produce and yield is often lower then non-miniaturized version of the same product. The higher cost and lower yield have affected how miniaturized products are developed and marketed. For example, it is uncommon to find full-page inkjet print heads.
One of many criticalities involved in miniaturized products is the manner of addressing individual elements, which may be identically structured, distributed in space. There are currently only a few methods of addressing these individual elements.
The first, and arguably the oldest, method is physical addressing wherein the means of physical interaction has a limited physical extent and that means itself is relocated to the region where the desired interaction is to take place. An example of this technique includes the CRT, where the identically structured elements are the screen phosphor dots and the means of interaction is the electron beam.
A second method is matrix addressing wherein each element is connected to two electrical circuit elements (so-called “row elements” and “column elements”), so that if a single row element is connected across a voltage source to a single column element, only a single of the elements experiences a voltage drop across its pair of connections. Examples of this technique include the LCD, the inkjet print head itself, and various memory devices.
Unfortunately, the problem with both of these methods, and other similar techniques, is that they don't scale well enough to deal with the numbers of elements, which may be identically structured, to be addressed as the technologies for producing and distributing these elements have advanced. It is already the case that expenses arising from interconnect requirements (e.g., pin count) dominate the cost of producing memory chips, and the physical difficulty and complexity of implementing the matrix addressing method limits the size of the apparatus to address only a small number of logical pixels at a time, e.g., capping the useable number of inkjet nozzles on a print head at about the current number found in most printers.
Additionally, as elements, which may be identically structured, e.g., nanochips, continue to be deployed in greater numbers and in ever smaller sizes, these traditional addressing methods are simply inadequate to handle the evolution of nano-scale circuitry. In fact, these addressing methods continue to be a limitation on the deployment of nano-scale technology.
Therefore, a need exists for a method and apparatus for controlling nano-scale circuitry.